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High Performance 2A and 3A LDOs
ISL80102, ISL80103
The ISL80102 and ISL80103 are low voltage, high-current, single output LDOs specified for 2A and 3A output current, respectively. These parts operate from input voltages of 2.2V to 6V and are capable of providing output voltages of 0.8V to 5V on the adjustable VOUT versions. Fixed output voltage options available in 0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5V. Other custom voltage options available upon request. For applications that demand in-rush current less than current limit, an external capacitor on the in-rush set pin provides adjustment. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. Sub-micron CMOS process is utilized for this product family to deliver the best in class analog performance and overall value. These CMOS LDOs will consume significantly lower quiescent current as a function of load over bipolar LDOs, which translates into higher efficiency and the ability to consider packages with smaller footprints. Quiescent current is modestly compromised to enable a leading class fast load transient response, and hence a lower total AC regulation band for an LDO in this category.
ISL80102, ISL80103
Features
* 0.5% initial VOUT Accuracy * Designed for 2.2V to 6V Input Supply * 1.8% Guaranteed VOUT Accuracy for Junction Temperature Range from -40C to +125C * 185mV Dropout @ 3A, 125mV Dropout @ 2A * Fast Load Transient Response * Rated Output Current Options of 2A and 3A * Adjustable In-Rush Current Limiting * Fixed and Adjustable VOUT Options Available * 65dB Typical PSRR * Output Noise of 100VRMS between 300Hz to 300kHz * PG Feature * 900mV Enable Input Threshold * Short-Circuit Current Protection * 1A Peak Reverse Current * Over-Temperature Shutdown * Any Cap Stable with Minimum 10F Ceramic * Available in a 10 Ld DFN Package and soon to follow TO220-5, TO263-5 and SOT223-5 (1A and 2A versions) * Pb-Free (RoHS Compliant)
Pin Configuration
ISL80102, ISL80103 (10 LD 3X3 DFN) TOP VIEW
VOUT VOUT SENSE/ADJ PG GND 1 2 3 4 5 10 VIN 9 VIN 8 DNC 7 ENABLE 6 SS
Applications*(see page 15)
* DSP, FPGA and P Core Power Supplies * Noise-Sensitive Instrumentation Systems * Post Regulation of Switched Mode Power Supplies * Industrial Systems * Medical Equipment * Telecommunications and Networking Equipment * Servers * Hard Disk Drives (HD/HDD)
September 30, 2009 FN6660.0
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
Pin Descriptions
PIN NUMBER 1, 2 3 4 5 6 7 8 9, 10 EPAD PIN NAME VOUT SENSE/ADJ PG GND SS ENABLE DNC VIN Output voltage pin. Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT. VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used. GND pin. External cap controls in-rush current. VIN independent chip enable. TTL and CMOS compatible. Do not connect this pin to ground or supply. Leave floating. Input supply pin. Must be soldered directly to GND plane DESCRIPTION
Block Diagram
VIN R4 M5 M4 IL/10,000 M3 M1 POWER PMOS IL VOUT R8 R7 R9 + EN EN + EN EN SS M7 V TO I + 500mV + 485mV + M2 R3 GND EN + 500mV R4 R2 ADJ PG LEVEL SHIFT
10A 10A
R1
SNS
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ISL80102, ISL80103
Typical Applications
2.5V 10% 10F 10k 9 10 VIN VIN V OUT V OUT SENSE/ADJ ISL80102 ISL80103 7 6 (*Note 12) ENABLE SS GND 5 4 1 2 3 10F 10 0k 1.8V 1.8%
PG
FIXED
FIGURE 1.
1 2 10 F 2.6k 10 0k SE NSE/ADJ 1k 7 6
2.5V 10% 10F
9 10
VIN VIN ISL80102 ISL80103
VOUT VOUT
1.8V 1.8%
10k
ENABLE PG SS GND 5 4
(*NOTE 12)
ADJUSTABLE
FIGURE 2.
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ISL80102, ISL80103
Ordering Information
PART NUMBER ISL80102IRAJZ (Notes 1, 3) ISL80102IR08Z (Notes 1, 3) ISL80102IR12Z (Notes 1, 3) ISL80102IR15Z (Notes 1, 3) ISL80102IR18Z (Notes 1, 3) ISL80102IR25Z (Notes 1, 3) ISL80102IR33Z (Notes 1, 3) ISL80102IR50Z (Notes 1, 3) ISL80103IRAJZ (Notes 1, 3) ISL80103IR08Z (Notes 1, 3) ISL80103IR12Z (Notes 1, 3) ISL80103IR15Z (Note 3) ISL80103IR15Z-T (Notes 2, 3) ISL80103IR18Z (Notes 1, 3) ISL80103IR25Z (Notes 1, 3) ISL80103IR33Z (Note 3) ISL80103IR33Z-T (Notes 2, 3) ISL80103IR50Z (Note 3) ISL80103IR50Z-T (Notes 2, 3) NOTES: 1. Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For other output voltages, contact Intersil Marketing. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on MSL please see techbrief TB363. PART MARKING DZJA DZKA DZLA DZMA DZNA DZPA DZRA DZSA DZAA DZBA DZCA DZDA DZDA DZEA DZFA DZGA DZGA DZHA DZHA VOUT VOLTAGE (Note 4) ADJ 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V ADJ 0.8V 1.2V 1.5V 1.5V 1.8V 2.5V 3.3V 3.3V 5.0V 5.0V TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN Tape and Reel 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN Tape and Reel 10 Ld 3x3 DFN 10 Ld 3x3 DFN Tape and Reel PKG DWG. # L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3 L10.3x3
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Absolute Maximum Ratings (Note 8)
VIN relative to GND . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V PG, ENABLE, SENSE/ADJ, SS Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld 3x3 DFN Package (Notes 6, 7) 45 4 Maximum Junction Temperature (Plastic Package). . . +150C Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Junction Temperature Range (TJ) . . VIN relative to GND . . . . . . . . . . . . VOUT range . . . . . . . . . . . . . . . . . . PG, ENABLE, SENSE/ADJ, SS relative PG sink current . . . . . . . . . . . . . . . . . . . . -40C to +125C . . . . . . . . . 2.2V to 6V . . . . . . . . 800mV to 5V to GND . . . . . 0V to 6V . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 7. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 8. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to "Application Section" on page 7 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40C to +125C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits. TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS
PARAMETER DC CHARACTERISTICS DC Output Voltage Accuracy
SYMBOL
VOUT
VOUT Options: 0.8V, 1.2V, 1.5V and 1.8V 2.2V < VIN < 3.6V; 0A < ILOAD < 3A VOUT Options: 2.5V, 3.3V and 5.0V VOUT + 0.4V < VIN < 6V; 0A < ILOAD < 3A -1.8 491 0.5 500 0.1 0.1 -0.8 -0.6 0.01 7.5 8.5 0.4 3.3 120 81 5.0 2.8 160 16 185 125 1 9 12 -1.8 509 0.4 0.8 % mV % % % % A mA mA A A mV mV A A C -1.8 0.5 1.8 %
Feedback Pin (ADJ option only) DC Input Line Regulation
VFB
2.2V < VIN < 6V, 0A < ILOAD < 3A
VOUT/VIN VOUT + 0.4V < VIN < 3.6V, VOUT = 1.8V VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
DC Output Load Regulation VOUT/IOU 0A < ILOAD < 3A, All voltage options
T
0A < ILOAD < 2A, All voltage options VADJ = 0.5V ILOAD = 0A, 2.2V < VIN < 6V ILOAD = 3A, 2.2V < VIN < 6V ENABLE Pin = 0.2V, VIN = 5V ENABLE Pin = 0.2V, VIN = 6V ILOAD = 3A, VOUT = 2.5V ILOAD = 2A, VOUT = 2.5V VOUT = 0V, VOUT + 0.4V < VIN < 6V VOUT = 0V, VOUT + 0.4V < VIN < 6V
Feedback Input Current Ground Pin Current IQ ISHDN VDO ISC
Ground Pin Current in Shutdown Dropout Voltage (Note 10)
Output Short Circuit Current (3A Version) Output Short Circuit Current (2A Version) Thermal Shutdown Temperature
TSD
VOUT + 0.4V < VIN < 6V
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FN6660.0 September 30, 2009
ISL80102, ISL80103
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to "Application Section" on page 7 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40C to +125C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits. (Continued) TEST CONDITIONS VOUT + 0.4V < VIN < 6V MIN (Note 9) TYP 15 MAX (Note 9) UNITS C
PARAMETER Thermal Shutdown Hysteresis (Rising Threshold) AC CHARACTERISTICS Input Supply Ripple Rejection Output Noise Voltage
SYMBOL
TSDn
PSRR
f = 1kHz, ILOAD = 1A; VIN = 2.2V f = 120Hz, ILOAD = 1A; VIN = 2.2V ILOAD = 10mA, BW = 300Hz < f < 300kHz 2.2V < VIN < 6V Must be independent of VIN, 2.2V < VIN < 6V COUT = 10F, ILOAD = 1A VIN = 6V, EN = 3V 0.3
55 62 100
dB
VRMS 0.95 V mV s 1 A
ENABLE PIN CHARACTERISTICS Turn-on Threshold Hysteresis (rising threshold) Enable Pin Turn-on Delay Enable Pin Leakage Current SOFT START CHARACTERISTICS In-rush Current Limit Adjust PG PIN CHARACTERISTICS VOUT PG Flag Threshold VOUT PG Flag Hysteresis PG Flag Low Voltage PG Flag Leakage Current NOTES: 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal value. 11. Electromigration specification defined as lifetime average junction temperature of +110C where max rated DC current = lifetime average current. 12. Minimum cap on VIN and VOUT required for stability. 13. Used when large bulk capacitance required on VOUT for application. ISINK = 500A VIN = 6V, PG = 6V 75 84 4 47 0.05 100 1 92 %VOUT % mV A RPD ICHG -7 323 -4.5 -2 A 0.8 135 150
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Application Section
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs is optimized for a true 2.5V to 1.8V conversion where the input supply can have a tolerance of as much as 10% for conditions noted in the "Electrical Specifications" table on page 5. Minimum guaranteed input voltage is 2.2V. However, due to the nature of an LDO, VIN must be some margin higher than the output voltage plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The Dropout spec of this family of LDOs has been generously specified in order to allow applications to design for a level of efficiency that can accommodate the smaller outline package for those applications that cannot accommodate the profile of the TO220/263.
circuit performs as a constant current source when the output current exceeds the current limit threshold noted in the "Electrical Specifications" table on page 5. If the short or overload condition is removed from VOUT, then the output returns to normal voltage mode regulation. In the event of an overload condition on the DFN package the LDO will begin to cycle on and off due to the die temperature exceeding thermal fault condition. The TO220/263 package will tolerate higher levels of power dissipation on the die which may never thermal cycle if the heatsink of this larger package can keep the die temperature below the specified typical thermal shutdown temperature.
Functional Description
Enable Operation
The Enable turn-on threshold is typically 770mV with a hysteresis of 135mV. The Enable pin doesn't have an internal pull-up or pull-down resistor. As a result, this pin must not be left floating. This pin must be tied to VIN if it is not used. A 1k to 10k pull-up resistor will be required for applications that use open collector or open drain outputs to control the Enable pin. The Enable pin may be connected directly to VIN for applications that are always on.
External Capacitor Requirements
GENERAL GUIDELINE External capacitors are required for proper operation. Careful attention must be paid to layout guidelines and selection of capacitor type and value to ensure optimal performance. OUTPUT CAPACITOR The required minimum output capacitor is 10F X5R/X7R to ensure stable operation. Lower cost Y5V and Z5U type ceramic capacitors are acceptable if the size of the capacitor is larger to compensate for the significantly lower tolerance over X5R/X7R types (approximately 2x). Additional capacitors of any value in Ceramic, POSCAP or Alum/Tantalum Electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. This minimum capacitor must be connected to VOUT and Ground pins of the LDO with PCB traces no longer than 0.5cm. INPUT CAPACITOR The minimum input capacitor required for proper operation is 10F having a ceramic dielectric. This minimum capacitor must be connected to VOUT and Ground pins of the LDO with PCB traces no longer than 0.5cm.
Soft-Start Operation
The soft start circuit controls the rate at which the output voltage comes up to regulation at power-up or coming out of a chip disable. A constant current charges an external soft start capacitor. The external capacitor always gets discharged to 0V at start-up of after coming out of a chip disable. The discharge rate is the RC time constant of RPD and CSS. The soft-start function effectively limits the amount of in-rush current below the programmed current limit during start-up or an enable sequence to avoid an overcurrent fault condition. This can be an issue for applications that require large, external bulk capacitances on VOUT where high levels of charging current can be seen for a significant period of time. High in-rush currents can cause VIN to drop below minimum which could cause VOUT to shutdown. Figure 3 shows the relationship between in-rush current and CSS with a COUT of 1000F.
5.0 IN-RUSH CURRENT LIMIT (A) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 Css (nF) 80 100
Thermal Fault Protection
In the event the die temperature exceeds typically +160C, then the output of the LDO will shut down until the die temperature can cool down to typically +145C. The level of power combined with the thermal impedance of the package (+50C/W for DFN) will determine if the junction temperature exceeds the thermal shutdown temperature specified in the "Electrical Specifications" table on page 5 (see thermal packaging guidelines).
Current Limit Protection
The ISL80102/3 family of LDOs incorporates protection against overcurrent due to any short or overload condition applied to the output pin. The current limit 7
FIGURE 3. IN-RUSH CURRENT vs SOFT-START CAPACITANCE
FN6660.0 September 30, 2009
ISL80102, ISL80103
Power-Good Operation
The PGOOD circuit monitors VOUT and signals a fault condition when VOUT is below 84% of the nominal output voltage. The PGOOD flag is an open-drain NMOS that can sink 10mA during a fault condition. The PGOOD pin requires an external pull up resistor which is typically connected to the VOUT pin. The PGOOD pin should not be pulled up to a voltage source greater than VIN. During a fault condition, the PGOOD output is pulled low. The PGOOD fault can be caused by the current limit fault or low input voltage. The PGOOD does not function during thermal shutdown and when the part is disabled. The maximum allowed junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) will determine the maximum allowed junction temperature rise (TJ) as shown in Equation 4:
T J = T J ( MAX ) - T A ( MAX ) (EQ. 4)
To calculate the maximum ambient operating temperature, use the junction-to-ambient thermal resistance (JA) for the DFN package with Equation 5:
P D ( MAX ) = ( T J ( MAX ) - T A ) JA (EQ. 5)
Output Voltage Selection
An external resistor divider is used to scale the output voltage relative to the internal reference voltage. This voltage is then fed back to the error amplifier. The output voltage can be programmed to any level between 0.8V and 5V. An external resistor divider, R1 and R2, is used to set the output voltage as shown in Equation 1. The recommended value for R2 is 500 to 1k. R1 is then chosen according to Equation 2:
R1 V OUT = 0.5V x ------ + 1 R2 (EQ. 1)
Substitute PD for PD(MAX) and the maximum ambient operating temperature can be found by solving for TA using Equation 6:
T A = T JMAX - P D ( MAX ) x JA (EQ. 6)
Heatsinking The DFN Package
The DFN package uses the copper area on the PCB as a heat-sink. The EPAD of this package must be soldered to the copper plane (GND plane) for heat sinking. Figure 4 shows a curve for the JA of the DFN package for different copper area sizes.
46 44 JA, C/W 42 40 38 36 34
2 4 6 8 10 12 14 16 18 20 22 2 EPAD-MOUNT COPPER LAND AREA ON PCB, mm 24
V OUT R 1 = R 2 x --------------- - 1 0.5V
(EQ. 2)
Power Dissipation
The junction temperature must not exceed the range specified in the Recommended Operating Conditions. The power dissipation can be calculated by using Equation 3:
P D = ( V IN - V OUT ) x I OUT + V IN x I GND (EQ. 3)
FIGURE 4. 3mmx3mm-10 Pin DFN ON 4-LAYER PCB WITH THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND AREA ON PCB
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Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A.
1.8 1.2 0.6 0 -0.6 -1.2 -1.8 -50 2.0 1.8 OUTPUT VOLTAGE (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 -25 0 25 50 75 100 125 JUNCTION TEMPERATURE (C) 150 0 0 1 3 2 4 SUPPLY VOLTAGE (V) 5 6 +25C -40C +125C
VOUT (%)
FIGURE 5. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 6. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8 1.2 VOUT (%) 0.6 0.0 -0.6 -1.2 -1.8 GROUND CURRENT (mA) 2.5 3.0
9 8 7 6 5 4 3 2 1 0 2 3 4 INPUT VOLTAGE (V) 5 6
+25C
-40C +125C
0 0.5 1.0 1.5 2.0 OUTPUT CURRENT (A)
FIGURE 7. OUTPUT VOLTAGE vs OUTPUT CURRENT
FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE
9.1 GROUND CURRENT (mA) 8.9 CURRENT (mA) 8.7 8.5 8.3 8.1 7.9 7.7 7.5 0 0.5 1.0 1.5 2.0 OUTPUT CURRENT (A) 2.5 3.0
12.0 11.5 11.0
-40C
-40C
10.5 10.0 9.5 9.0 8.5 8.0 7.5 0.8 1.4
+25C +125C
+125C +25C
2.0 2.6 3.2 3.8 OUTPUT VOLTAGE (V) 4.4 5.0
FIGURE 9. GROUND CURRENT vs OUTPUT CURRENT
FIGURE 10. GROUND CURRENT vs OUTPUT VOLTAGE
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FN6660.0 September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued)
5.0 4.5 GROUND CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -25 -10 5 VIN = 5V 20 35 50 65 80 95 110 125 TEMPERATURE (C) GROUND CURRENT (A) 12 11 10 9 8 7 6 5 4 3 2 1 0 -40 -25 -10
VIN = 6V 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
FIGURE 11. SHUTDOWN CURRENT vs TEMPERATURE
FIGURE 12. SHUTDOWN CURRENT vs TEMPERATURE
150 140 130 120 110 2A 100 90 3A 80 70 60 50 40 30 20 1A 10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
0
0.5
1.0 1.5 2.0 OUTPUT CURRENT (A)
2.5
3.0
FIGURE 13. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90 0.85 0.80 0.75 VOLTAGE (V) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (C) PG (1V/DIV) TIME (10ms/DIV) VOUT (1V/DIV) SS (1V/DIV) VIN (1V/DIV)
FIGURE 15. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE
FIGURE 16. POWER-UP (VIN = 2.2V)
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FN6660.0 September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued)
EN (1V/DIV) VIN (1V/DIV) SS (1V/DIV) SS (1V/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
PG (1V/DIV) TIME (10ms/DIV)
PG (1V/DIV) TIME (50s/DIV)
FIGURE 17. POWER-DOWN (VIN = 2.2V)
FIGURE 18. ENABLE START-UP
300 EN (1V/DIV) START-UP TIME (s) 250 200 150 100 50 0 2.0
SS (1V/DIV)
VOUT (1V/DIV)
PG (1V/DIV) TIME (5ms/DIV)
2.5
3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V)
5.5
6.0
FIGURE 19. ENABLE SHUTDOWN
FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE
300 250 200 150 100 50 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (C)
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -25 -10
START-UP TIME (s)
CURRENT LIMIT (A)
ISL80103
ISL80102
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (C)
FIGURE 21. START-UP TIME vs TEMPERATURE
FIGURE 22. CURRENT LIMIT vs TEMPERATURE
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FN6660.0 September 30, 2009
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Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued)
6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0
CURRENT LIMIT (A)
ISL80103
VOUT (1V/DIV)
ISL80102
2.5
3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V)
5.5
6.0
IOUT (1A/DIV) TIME (10ms/DIV)
FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80102)
VOUT (1V/DIV)
VOUT (1V/DIV)
IOUT (1A/DIV) TIME (100ms/DIV)
IOUT (2A/DIV) TIME (20ms/DIV)
FIGURE 25. THERMAL CYCLING (ISL80102)
FIGURE 26. CURRENT LIMIT RESPONSE (ISL80103)
EN (1V/DIV)
VOUT (1V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
VOUT (1V/DIV)
TIME (50ms/DIV)
TIME (1ms/DIV)
FIGURE 27. THERMAL CYCLING (ISL80103)
FIGURE 28. IN-RUSH CURRENT WITH NO SOFT-START CAPACITOR, COUT = 1000F
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FN6660.0 September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued)
EN (1V/DIV) EN (1V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
TIME (1ms/DIV)
TIME (1ms/DIV)
FIGURE 29. IN-RUSH WITH 22nF SOFT-START CAPACITOR, COUT = 1000F
FIGURE 30. IN-RUSH WITH 47nF SOFT-START CAPACITOR, COUT = 1000F
VOUT (50mV/DIV)
VOUT (50mV/DIV)
3A
3A
0A IOUT (2A/DIV) TIME (100s/DIV)
0A IOUT (2A/DIV) TIME (100s/DIV)
FIGURE 31. LOAD TRANSIENT 0A TO 3A, COUT = 10F CERAMIC
FIGURE 32. LOAD TRANSIENT 0A TO 3A, COUT = 10F CERAMIC + 100F OSCON
VOUT (50mV/DIV)
VOUT (50mV/DIV)
3A 1A
IOUT (2A/DIV) 1A
3A IOUT (2A/DIV)
TIME (100s/DIV)
TIME (100s/DIV)
FIGURE 33. LOAD TRANSIENT 1A TO 3A, COUT = 10F CERAMIC
FIGURE 34. LOAD TRANSIENT 1A TO 3A, COUT = 10F CERAMIC + 100F OSCON
13
FN6660.0 September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued)
3.2V 80 2.2V VIN (1V/DIV) 70 60 50 dB 40 30 20 VOUT (10mV/DIV) 10 0 TIME (200s/DIV) 10 100 1k 10k FREQUENCY (Hz) 100k 1M 1A 100mA
FIGURE 35. LINE TRANSIENT
FIGURE 36. PSRR vs LOAD
80 70 60 50 dB 40 30 20 10 IL = 100mA 100 1k 10k FREQUENCY (Hz) 100k 1M 10F 47F dB 100F
80 70 60 50 40 30 20 10 0 10 IL = 1A 100 1k 10k FREQUENCY (Hz) 100k 1M 2.2V 2V 2.5V
0 10
FIGURE 37. PSRR vs COUT
FIGURE 38. PSRR vs VIN
10
NOISE V/Hz
1
0.1
0.01 10
100
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 39. SPECTRAL NOISE DENSITY vs FREQUENCY
14
FN6660.0 September 30, 2009
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 09/30/09 REVISION FN6660.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL80102, ISL80103 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6660.0 September 30, 2009
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09
3.00 A B 1 6 PIN 1 INDEX AREA 2 2.00 8x 0.50 3.00 6 PIN #1 INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
TOP VIEW
10x 0.35 4 (4X) 0.10 M C A B
BOTTOM VIEW
0.415 0.23
PACKAGE OUTLINE (10x 0.23) 1.00 MAX
(10 x 0.55)
0.35
0.200
SEE DETAIL "X" 0.10 C C BASE PLANE 0.20 SIDE VIEW SEATING PLANE 0.08 C
(8x 0.50) C 1.60 0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Lead width applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 0.20 REF 5
2.00
2. 3. 4.
16
FN6660.0 September 30, 2009

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